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Miscellany
Saturday, April 19th, 2008 at 7:10:03pm UTC 

  1. Asuka i2c # cat ../../include/asm-arm/arch-mx31/mx31-regs.h
  2. /*
  3.  *
  4.  * (c) 2007 Pengutronix, Sascha Hauer <[email protected]>
  5.  *
  6.  * See file CREDITS for list of people who contributed to this
  7.  * project.
  8.  *
  9.  * This program is free software; you can redistribute it and/or
  10.  * modify it under the terms of the GNU General Public License as
  11.  * published by the Free Software Foundation; either version 2 of
  12.  * the License, or (at your option) any later version.
  13.  *
  14.  * This program is distributed in the hope that it will be useful,
  15.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17.  * GNU General Public License for more details.
  18.  *
  19.  * You should have received a copy of the GNU General Public License
  20.  * along with this program; if not, write to the Free Software
  21.  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22.  * MA 02111-1307 USA
  23.  */
  24.  
  25. #ifndef __ASM_ARCH_MX31_REGS_H
  26. #define __ASM_ARCH_MX31_REGS_H
  27.  
  28. #define __REG(x)     (*((volatile u32 *)(x)))
  29. #define __REG16(x)   (*((volatile u16 *)(x)))
  30. #define __REG8(x)    (*((volatile u8 *)(x)))
  31.  
  32. #define CCM_BASE        0x53f80000
  33. #define CCM_CCMR        (CCM_BASE + 0x00)
  34. #define CCM_PDR0        (CCM_BASE + 0x04)
  35. #define CCM_PDR1        (CCM_BASE + 0x08)
  36. #define CCM_RCSR        (CCM_BASE + 0x0c)
  37. #define CCM_MPCTL       (CCM_BASE + 0x10)
  38. #define CCM_UPCTL       (CCM_BASE + 0x10)
  39. #define CCM_SPCTL       (CCM_BASE + 0x18)
  40. #define CCM_COSR        (CCM_BASE + 0x1C)
  41.  
  42. #define CCMR_MDS        (1 << 7)
  43. #define CCMR_SBYCS      (1 << 4)
  44. #define CCMR_MPE        (1 << 3)
  45. #define CCMR_PRCS_MASK  (3 << 1)
  46. #define CCMR_FPM        (1 << 1)
  47. #define CCMR_CKIH       (2 << 1)
  48.  
  49. #define PDR0_CSI_PODF(x)        (((x) & 0x1ff) << 23)
  50. #define PDR0_PER_PODF(x)        (((x) & 0x1f) << 16)
  51. #define PDR0_HSP_PODF(x)        (((x) & 0x7) << 11)
  52. #define PDR0_NFC_PODF(x)        (((x) & 0x7) << 8)
  53. #define PDR0_IPG_PODF(x)        (((x) & 0x3) << 6)
  54. #define PDR0_MAX_PODF(x)        (((x) & 0x7) << 3)
  55. #define PDR0_MCU_PODF(x)        ((x) & 0x7)
  56.  
  57. #define PLL_PD(x)               (((x) & 0xf) << 26)
  58. #define PLL_MFD(x)              (((x) & 0x3ff) << 16)
  59. #define PLL_MFI(x)              (((x) & 0xf) << 10)
  60. #define PLL_MFN(x)              (((x) & 0x3ff) << 0)
  61.  
  62. #define WEIM_BASE       0xb8002000
  63. #define CSCR_U(x)       (WEIM_BASE + (x) * 0x10)
  64. #define CSCR_L(x)       (WEIM_BASE + 4 + (x) * 0x10)
  65. #define CSCR_A(x)       (WEIM_BASE + 8 + (x) * 0x10)
  66.  
  67. #define IOMUXC_BASE     0x43FAC000
  68. #define IOMUXC_GPR      (IOMUXC_BASE + 0x8)
  69. #define IOMUXC_SW_MUX_CTL(x)    (IOMUXC_BASE + 0xc + (x) * 4)
  70. #define IOMUXC_SW_PAD_CTL(x)    (IOMUXC_BASE + 0x154 + (x) * 4)
  71.  
  72. #define IPU_BASE                0x53fc0000
  73. #define IPU_CONF                IPU_BASE
  74.  
  75. #define IPU_CONF_PXL_ENDIAN     (1<<8)
  76. #define IPU_CONF_DU_EN          (1<<7)
  77. #define IPU_CONF_DI_EN          (1<<6)
  78. #define IPU_CONF_ADC_EN         (1<<5)
  79. #define IPU_CONF_SDC_EN         (1<<4)
  80. #define IPU_CONF_PF_EN          (1<<3)
  81. #define IPU_CONF_ROT_EN         (1<<2)
  82. #define IPU_CONF_IC_EN          (1<<1)
  83. #define IPU_CONF_SCI_EN         (1<<0)
  84.  
  85. #define WDOG_BASE               0x53FDC000
  86.  
  87. /*
  88.  * Signal Multiplexing (IOMUX)
  89.  */
  90.  
  91. /* bits in the SW_MUX_CTL registers */
  92. #define MUX_CTL_OUT_GPIO_DR     (0 << 4)
  93. #define MUX_CTL_OUT_FUNC        (1 << 4)
  94. #define MUX_CTL_OUT_ALT1        (2 << 4)
  95. #define MUX_CTL_OUT_ALT2        (3 << 4)
  96. #define MUX_CTL_OUT_ALT3        (4 << 4)
  97. #define MUX_CTL_OUT_ALT4        (5 << 4)
  98. #define MUX_CTL_OUT_ALT5        (6 << 4)
  99. #define MUX_CTL_OUT_ALT6        (7 << 4)
  100. #define MUX_CTL_IN_NONE         (0 << 0)
  101. #define MUX_CTL_IN_GPIO         (1 << 0)
  102. #define MUX_CTL_IN_FUNC         (2 << 0)
  103. #define MUX_CTL_IN_ALT1         (4 << 0)
  104. #define MUX_CTL_IN_ALT2         (8 << 0)
  105.  
  106. #define MUX_CTL_FUNC            (MUX_CTL_OUT_FUNC | MUX_CTL_IN_FUNC)
  107. #define MUX_CTL_ALT1            (MUX_CTL_OUT_ALT1 | MUX_CTL_IN_ALT1)
  108. #define MUX_CTL_ALT2            (MUX_CTL_OUT_ALT2 | MUX_CTL_IN_ALT2)
  109. #define MUX_CTL_GPIO            (MUX_CTL_OUT_GPIO_DR | MUX_CTL_IN_GPIO)
  110.  
  111. /* Register offsets based on IOMUXC_BASE */
  112. /* 0x00 .. 0x7b */
  113. #define MUX_CTL_RTS1            0x7c
  114. #define MUX_CTL_CTS1            0x7d
  115. #define MUX_CTL_DTR_DCE1        0x7e
  116. #define MUX_CTL_DSR_DCE1        0x7f
  117. #define MUX_CTL_CSPI2_SCLK      0x80
  118. #define MUX_CTL_CSPI2_SPI_RDY   0x81
  119. #define MUX_CTL_RXD1            0x82
  120. #define MUX_CTL_TXD1            0x83
  121. #define MUX_CTL_CSPI2_MISO      0x84
  122. /* 0x85 .. 0x8a */
  123. #define MUX_CTL_CSPI2_MOSI      0x8b
  124.  
  125. /* The modes a specific pin can be in
  126.  * these macros can be used in mx31_gpio_mux() and have the form
  127.  * MUX_[contact name]__[pin function]
  128.  */
  129. #define MUX_RXD1__UART1_RXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_RXD1)
  130. #define MUX_TXD1__UART1_TXD_MUX ((MUX_CTL_FUNC << 8) | MUX_CTL_TXD1)
  131. #define MUX_RTS1__UART1_RTS_B   ((MUX_CTL_FUNC << 8) | MUX_CTL_RTS1)
  132. #define MUX_RTS1__UART1_CTS_B   ((MUX_CTL_FUNC << 8) | MUX_CTL_CTS1)
  133.  
  134. #define MUX_CSPI2_MOSI__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MOSI)
  135. #define MUX_CSPI2_MISO__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO)
  136.  
  137.  
  138. #endif /* __ASM_ARCH_MX31_REGS_H */
  139.  
  140.  
  141.  
  142.  
  143.  
  144.  
  145. Asuka i2c # cat mxc_i2c.c
  146. /*
  147.  * i2c driver for Freescale mx31
  148.  *
  149.  * (c) 2007 Pengutronix, Sascha Hauer <[email protected]>
  150.  *
  151.  * See file CREDITS for list of people who contributed to this
  152.  * project.
  153.  *
  154.  * This program is free software; you can redistribute it and/or
  155.  * modify it under the terms of the GNU General Public License as
  156.  * published by the Free Software Foundation; either version 2 of
  157.  * the License, or (at your option) any later version.
  158.  *
  159.  * This program is distributed in the hope that it will be useful,
  160.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  161.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  162.  * GNU General Public License for more details.
  163.  *
  164.  * You should have received a copy of the GNU General Public License
  165.  * along with this program; if not, write to the Free Software
  166.  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  167.  * MA 02111-1307 USA
  168.  */
  169.  
  170. #include <common.h>
  171.  
  172. #if defined(CONFIG_HARD_I2C) && defined (CONFIG_I2C_MXC)
  173.  
  174. #include <asm/arch/mx31.h>
  175. #include <asm/arch/mx31-regs.h>
  176.  
  177. #define IADR    0x00
  178. #define IFDR    0x04
  179. #define I2CR    0x08
  180. #define I2SR    0x0c
  181. #define I2DR    0x10
  182.  
  183. #define I2CR_IEN        (1 << 7)
  184. #define I2CR_IIEN       (1 << 6)
  185. #define I2CR_MSTA       (1 << 5)
  186. #define I2CR_MTX        (1 << 4)
  187. #define I2CR_TX_NO_AK   (1 << 3)
  188. #define I2CR_RSTA       (1 << 2)
  189.  
  190. #define I2SR_ICF        (1 << 7)
  191. #define I2SR_IBB        (1 << 5)
  192. #define I2SR_IIF        (1 << 1)
  193. #define I2SR_RX_NO_AK   (1 << 0)
  194.  
  195. #ifdef CFG_I2C_MX31_PORT1
  196. #define I2C_BASE        0x43f80000
  197. #elif defined (CFG_I2C_MX31_PORT2)
  198. #define I2C_BASE        0x43f98000
  199. #elif defined (CFG_I2C_MX31_PORT3)
  200. #define I2C_BASE        0x43f84000
  201. #else
  202. #error "define CFG_I2C_MX31_PORTx to use the mx31 I2C driver"
  203. #endif
  204.  
  205. #ifdef DEBUG
  206. #define DPRINTF(args...)  printf(args)
  207. #else
  208. #define DPRINTF(args...)
  209. #endif
  210.  
  211. static u16 div[] = { 30, 32, 36, 42, 48, 52, 60, 72, 80, 88, 104, 128, 144,
  212.                      160, 192, 240, 288, 320, 384, 480, 576, 640, 768, 960,
  213.                      1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840};
  214.  
  215. void i2c_init(int speed, int unused)
  216. {
  217.         int freq = mx31_get_ipg_clk();
  218.         int i;
  219.  
  220.         for (i = 0; i < 0x1f; i++)
  221.                 if (freq / div[i] <= speed)
  222.                         break;
  223.  
  224.         DPRINTF("%s: speed: %d\n",__FUNCTION__, speed);
  225.  
  226.         __REG16(I2C_BASE + I2CR) = 0; /* Reset module */
  227.         __REG16(I2C_BASE + IFDR) = i;
  228.         __REG16(I2C_BASE + I2CR) = I2CR_IEN;
  229.         __REG16(I2C_BASE + I2SR) = 0;
  230. }
  231.  
  232. static int wait_busy(void)
  233. {
  234.         int timeout = 10000;
  235.  
  236.         while (!(__REG16(I2C_BASE + I2SR) & I2SR_IIF) && --timeout)
  237.                 udelay(1);
  238.         __REG16(I2C_BASE + I2SR) = 0; /* clear interrupt */
  239.  
  240.         return timeout;
  241. }
  242.  
  243. static int tx_byte(u8 byte)
  244. {
  245.         __REG16(I2C_BASE + I2DR) = byte;
  246.  
  247.         if (!wait_busy() || __REG16(I2C_BASE + I2SR) & I2SR_RX_NO_AK)
  248.                 return -1;
  249.         return 0;
  250. }
  251.  
  252. static int rx_byte(void)
  253. {
  254.         if (!wait_busy())
  255.                 return -1;
  256.  
  257.         return __REG16(I2C_BASE + I2DR);
  258. }
  259.  
  260. int i2c_probe(uchar chip)
  261. {
  262.         int ret;
  263.  
  264.         __REG16(I2C_BASE + I2CR) = 0; /* Reset module */
  265.         __REG16(I2C_BASE + I2CR) = I2CR_IEN;
  266.  
  267.         __REG16(I2C_BASE + I2CR) = I2CR_IEN |  I2CR_MSTA | I2CR_MTX;
  268.         ret = tx_byte(chip << 1);
  269.         __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MTX;
  270.  
  271.         return ret;
  272. }
  273.  
  274. static int i2c_addr(uchar chip, uint addr, int alen)
  275. {
  276.         __REG16(I2C_BASE + I2SR) = 0; /* clear interrupt */
  277.         __REG16(I2C_BASE + I2CR) = I2CR_IEN |  I2CR_MSTA | I2CR_MTX;
  278.  
  279.         if (tx_byte(chip << 1))
  280.                 return -1;
  281.  
  282.         while (alen--)
  283.                 if (tx_byte((addr >> (alen * 8)) & 0xff))
  284.                         return -1;
  285.         return 0;
  286. }
  287.  
  288. int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
  289. {
  290.         int timeout = 10000;
  291.         int ret;
  292.  
  293.         DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n",__FUNCTION__, chip, addr, alen, len);
  294.  
  295.         if (i2c_addr(chip, addr, alen)) {
  296.                 printf("i2c_addr failed\n");
  297.                 return -1;
  298.         }
  299.  
  300.         __REG16(I2C_BASE + I2CR) = I2CR_IEN |  I2CR_MSTA | I2CR_MTX | I2CR_RSTA;
  301.  
  302.         if (tx_byte(chip << 1 | 1))
  303.                 return -1;
  304.  
  305.         __REG16(I2C_BASE + I2CR) = I2CR_IEN |  I2CR_MSTA | ((len == 1) ? I2CR_TX_NO_AK : 0);
  306.  
  307.         ret = __REG16(I2C_BASE + I2DR);
  308.  
  309.         while (len--) {
  310.                 if ((ret = rx_byte()) < 0)
  311.                         return -1;
  312.                 *buf++ = ret;
  313.                 if (len <= 1)
  314.                         __REG16(I2C_BASE + I2CR) = I2CR_IEN |  I2CR_MSTA | I2CR_TX_NO_AK;
  315.         }
  316.  
  317.         wait_busy();
  318.  
  319.         __REG16(I2C_BASE + I2CR) = I2CR_IEN;
  320.  
  321.         while (__REG16(I2C_BASE + I2SR) & I2SR_IBB && --timeout)
  322.                 udelay(1);
  323.  
  324.         return 0;
  325. }
  326.  
  327. int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
  328. {
  329.         int timeout = 10000;
  330.         DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n",__FUNCTION__, chip, addr, alen, len);
  331.  
  332.         if (i2c_addr(chip, addr, alen))
  333.                 return -1;
  334.  
  335.         while (len--)
  336.                 if (tx_byte(*buf++))
  337.                         return -1;
  338.  
  339.         __REG16(I2C_BASE + I2CR) = I2CR_IEN;
  340.  
  341.         while (__REG16(I2C_BASE + I2SR) & I2SR_IBB && --timeout)
  342.                 udelay(1);
  343.  
  344.         return 0;
  345. }
  346.  
  347. #endif /* CONFIG_HARD_I2C */

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