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- Anonymous
- Sunday, November 11th, 2007 at 9:40:33am MST
- Index: firmware/app.lds
- ===================================================================
- --- firmware/app.lds (revision 15577)
- +++ firmware/app.lds (working copy)
- @@ -60,9 +60,8 @@
- #define IRAMSIZE 0x7000
- #elif CONFIG_CPU==S3C2440
- #define DRAMORIG 0x00000100 + STUBOFFSET
- -#define IRAMORIG DRAMORIG
- +#define IRAMORIG 0x40000000
- #define IRAMSIZE 0x1000
- -#define IRAM DRAM
- #elif CONFIG_CPU==DM320
- #define DRAMORIG 0x00900000 + STUBOFFSET
- #define IRAMORIG 0x00000000
- @@ -86,9 +85,7 @@
- MEMORY
- {
- DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
- -#if CONFIG_CPU != S3C2440
- IRAM : ORIGIN = IRAMORIG, LENGTH = IRAMSIZE
- -#endif
- #if CONFIG_CPU==PNX0101
- IRAM0 : ORIGIN = IRAM0ORIG, LENGTH = IRAM0SIZE
- #endif
- @@ -182,7 +179,94 @@
- _end = .;
- } > DRAM
- -#else /* End DM320 */
- +#elif CONFIG_CPU==S3C2440
- + .text :
- + {
- + loadaddress = .;
- + _loadaddress = .;
- + . = ALIGN(0x200);
- + *(.init.text)
- + *(.text*)
- + *(.glue_7)
- + *(.glue_7t)
- + . = ALIGN(0x4);
- + } > DRAM
- +
- + .rodata :
- + {
- + *(.rodata) /* problems without this, dunno why */
- + *(.rodata*)
- + *(.rodata.str1.1)
- + *(.rodata.str1.4)
- + . = ALIGN(0x4);
- +
- + /* Pseudo-allocate the copies of the data sections */
- + _datacopy = .;
- + } > DRAM
- +
- + /* TRICK ALERT! For RAM execution, we put the .data section at the
- + same load address as the copy. Thus, we don't waste extra RAM
- + when we don't actually need the copy. */
- + .data : AT ( _datacopy )
- + {
- + _datastart = .;
- + *(.data*)
- + . = ALIGN(0x4);
- + _dataend = .;
- + } > DRAM
- +
- + /DISCARD/ :
- + {
- + *(.eh_frame)
- + }
- +
- + .vectors 0x0 :
- + {
- + _vectorsstart = .;
- + *(.vectors);
- + _vectorsend = .;
- + } AT> DRAM
- +
- + _vectorscopy = LOADADDR(.vectors);
- +
- + .iram IRAMORIG :
- + {
- + _iramstart = .;
- + *(.icode)
- + *(.irodata)
- + *(.idata)
- + _iramend = .;
- + } > IRAM AT> DRAM
- +
- + _iramcopy = LOADADDR(.iram);
- +
- + .ibss (NOLOAD) :
- + {
- + _iedata = .;
- + *(.ibss)
- + . = ALIGN(0x4);
- + _iend = .;
- + } > DRAM
- +
- + .stack ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram) + SIZEOF(.vectors):
- + {
- + *(.stack)
- + stackbegin = .;
- + . += 0x2000;
- + stackend = .;
- + } > DRAM
- +
- + .bss :
- + {
- + _edata = .;
- + *(.bss*)
- + *(COMMON)
- + . = ALIGN(0x4);
- + _end = .;
- + } > DRAM
- +
- +#else /* End CONFIG_CPU */
- +
- #if !defined(CPU_ARM)
- .vectors :
- {
- @@ -241,11 +325,7 @@
- }
- #if defined(CPU_ARM)
- -#if CONFIG_CPU==DM320
- - .vectors IRAMORIG :
- -#else
- .vectors 0x0 :
- -#endif
- {
- _vectorsstart = .;
- *(.vectors);
- @@ -253,8 +333,6 @@
- #if CONFIG_CPU==PNX0101
- *(.dmabuf)
- } >IRAM0 AT> DRAM
- -#elif CONFIG_CPU==DM320
- - } > IRAM AT> DRAM
- #else
- } AT> DRAM
- #endif
- @@ -264,8 +342,6 @@
- #if CONFIG_CPU==PNX0101
- .iram IRAMORIG + SIZEOF(.vectors) :
- -#elif CONFIG_CPU==S3C2440 || CONFIG_CPU==DM320
- - .iram :
- #else
- .iram IRAMORIG :
- #endif
- @@ -325,7 +401,7 @@
- #if defined(CPU_COLDFIRE)
- .bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram):
- -#elif defined(CPU_ARM) && CONFIG_CPU != S3C2440
- +#elif defined(CPU_ARM)
- .bss ADDR(.data) + SIZEOF(.data) + SIZEOF(.iram) + SIZEOF(.vectors):
- #else
- .bss :
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